GFET-S10 (Die size 10 mm x 10 mm) - Processed in Clean Room Class 1000
The GFET-S10 chip from Graphenea provides 36 graphene devices distributed in a grid pattern on the chip. Thirty devices have a Hall-bar geometry and six have a 2-probe geometry. The Hall-bar devices can be used for Hall-bar measurements as well as 4-probe and 2-probe devices. There are varying graphene channel dimensions to allow investigation of geometry dependence on device properties.
The new version replaces Ni/Al contacts by Cr/Au, which are more inert and stable.
TYPICAL SPECIFICATIONS
Growth method: CVD synthesis
Chip dimensions: 10 mm x 10 mm
Chip thickness: 675 m
Number of GFETs per chip: 36
Gate oxide thickness: 90 nm
Gate oxide material: SiO2
Dielectric Constant of the SiO2 layer: 3.9
Resistivity of substrate: 1-10 .cm
Metallization: Chromium/Gold 2/50nm
Graphene field-effect mobility: >1000 cm2/V.s
Dirac point: <50 V
Minimum working devices: >75 %
ABSOLUTE MAXIMUM RATINGS
Maximum gate-source voltage: 50 V
Maximum temperature rating: 150 C
Maximum drain-source current density 107A.cm-2
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